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| PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Features * PLL clock distribution optimized for DDR2 SDRAM applications. * Distributes one differential clock input pair to ten differential clock output pairs. * Differential Inputs (CLK, CLK) and (FBIN, FBIN) * Input OE/OS: LVCMOS * Differential Outputs (Y[0:9], Y[0:9] and (FBOUT, FBOUT) * External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input. * Operates at AVDD = 1.8V for core circuit and internal PLL, and VDDQ = 1.8V for differential output drivers * Packaging (Pb-free & Green available): - 52-ball VFBGA (NF) Description PI6CU877 PLL clock driver is developed for Registered DDR2 DIMM applications with 1.8V operation and differential data input and output levels. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to eleven differential pairs of clock outputs which includes feedback clock (Y[0:9], Y[0:9]; FBOUT, FBOUT). The clock outputs are controlled by CLK/CLK, FBOUT, FBOUT, the LVCMOS (OE, OS) and the Analog Power input (AVDD). When OE is LOW the outputs except FBOUT, FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS is a program pin that must be tied to GND or VDD. When OS is high, OE will function as described above. When OS is LOW, OE has no effect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When CLK/CLK are logic low, the device will enter a low power mode. An input logic detection circuit will detect the logic low level and perform a low power state where all Y[0:9], Y[0:9]; FBOUT, FBOUT, and PLL are OFF. 3 Y0 GND NB VDDQ NB NB VDDQ NB GND Y4 Pin Configuration 1 A B C D E F G H J k Y1 Y1 Y2 Y2 CK CK AGND AVDD Y3 Y3 2 Y0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND Y4 4 Y5 GND NB VDDQ NB NB VDDQ NB GND Y9 5 Y5 GND GND OS VDDQ OE VDDQ GND GND Y9 6 Y6 Y6 Y7 Y7 FBIN FBIN FBOUT FBOUT Y8 Y8 PI6CU877 is a high performance, low skew, and low jitter PLL clock driver, and it is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. 1 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Block Diagram Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 CK CK OE OS AVDD LD* or OE Powerdown LD*, OS or OE Control & Test Logic PLL bypass LD* Y5 Y6 PLL 10K - 100k FBIN FBIN Y6 Y7 Y7 Y8 Y8 Y9 * The Logic Detect (LD) powers down the device when a logic low is applied to both CK and CK. Y9 FBOUT FBOUT 2 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Pinout Table Pin Name AGND AVDD CK CK FBIN FBIN FBOUT FBOUT OE OS GND VDDQ Y[0:9] Y[0:9] NB Characteristics Ground 1.8V nominal Differential Input Differential Input Differential Input Differential Input Differenital Output Differential Output LVCMOS input LVCMOS input Ground 1.8V nominal Differential Outputs Differential Outputs Analog ground Analog power Clock input with a (10K - 100K) pulldown resistor Complementary clock input with a (10K - 100K) pulldown resistor Complementary feedback clock input Feedback clock input Complementary Feedback clock output Feedback clock output Output enable (async.) Output select (tied to GND or VDDQ) Ground Logic and output power Clock outputs Complementary clock outputs No Ball (VFBGA only) Desctription Function Table Inputs AVDD GND GND GND GND 1.8V (nom) 1.8V (nom) 1.8V (nom) 1.8V (nom) 1.8V (nom) 1.8V (nom) OE H H L L L L H H X X OS X X H L H L X X X X CK L H L H L H L H L H CK H L H L H L H L L H Y L H L(Z)(1) L(Z)(1), Y7 active L(Z)(1) Y7 active L H L(Z)(1) L(Z)(1), Y H L L(Z)(1) L(Z)(1), Y7 active L(Z)(1) Y7 active H L L(Z)(1) L(Z)(1), Outputs FBOUT L H L H L H L H L(Z)(1) Reserved FBOUT H L H L H L H L L(Z)(1) PLL State Bypass/Off Bypass/Off Bypass/Off Bypass/Off On On On On Off Notes: 1. L(Z) means the outputs are disabled to a low state meeting the IODL limit on DC Specification 3 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Absolute Maximum Ratings (Over operating free-air temperature range) Symbol VDDQ, AVDD VI VO IIK IOK IO IO(PWR) TSTG Input voltage range Output voltage range Input clamp current Output clamp current Continuous output current Continuous current through each VDDQ or GND Storage temperature Parameter I/O supply voltage range and analog /core supply voltage range Min. -0.5 -0.5 -0.5 -50 -50 -50 -100 -65 50 50 50 100 150 C mA Max. 2.5 VDDQ +0.5 V Units Note: 1. Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. DC Specifications Recommended Operating Conditions Symbol VDDQ AVDD VIL VIH IOH IOL VIX VIN VID TA Output supply Voltage Supply voltage(4) OE, OS, CK, CK OE, OS, CK, CK 0.65 x VDDQ (VDDQ/2) -0.15 -0.3 DC AC 0.3 0.6 0 -9 9 (VDDQ/2) -0.15 VDDQ +0.3 VDDQ +0.4 VDDQ +0.4 70 C V mA Low-level input voltage(5) High-level input voltage(5) High-level output current, see Fig 2 Low-level output current, see Fig. 2 Input differential-pair crossing voltage Input voltage level Input differenital voltage, See Fig 9 (5) Operating free air temperature Parameter Min. 1.7 Typ. 1.8 VDDQ 0.35 x VDDQ V Max. 1.9 Units Notes: 4. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing parameters are guaranteed. 5. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK and CK, VIH and VIL limits are used to define the DC low and high levels for the logic detect state. 4 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Timing Requirements (Over recommended operating free-air temperature) Symbol FCK tDC tL tOFF Decription Operation clock frequency(7, 8) Application clock Stabalization frequency(7, 9) Input clock duty cycle time(10) down(10) Device power AVDD, VDDQ = 1.8V 0.1V Min. 25 160 40 Max. 300 270 60 15 8 Units MHz % s ns Notes: 7. The PLL is able to handle spread spectrum induced skew. 8. Operating clock frequency indicates a range over which the PLL is able to lock, but in which it is not required to meet the other timing parameters. (Used for low-speed debug). 9. Application clock frequency indicates a range over which the PLL must meet all timing parameters. 10. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up . During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK maybe left floating after they have been driven low for one complete clock cycle. DC Specifications Parameter VIK VOH IODL VOD II IDDLD IDD All Inputs HIGH output voltage Output disabled low current Description Test Condition II= -18mA IOH = -100A IOH = -9mA OE = L, VODL = 100mV 1.7V Output differenital voltage, the magniture of the difference between the true and complimentary outputs, see fig. 9 for dimentions CK, CK OE, OS, FBIN, FBIN Static Supple current, IDDQ + IADD Dynamic supply current, IDDQ + IADD, see note 6 for CPD calculation CK, CK FBIN, FBIN CK, CK FBIN, FBIN VI = VDDQ or GND VI = VDDQ or GND CK and CK = L CK and CK = 270MHz, all outputs are open (not connected to a PCB) VI = VDDQ or GND VI = VDDQ or GND VI = VDDQ or GND VI = VDDQ or GND 1.8V 1.9V AVDD, VDDQ 1.7V 1.7 to 1.9V 1.7 VDDQ -0.2 1.1 100 0.6 250 10 500 300 2 2 3 3 0.25 0.25 pF mA A A V Min. Typ. Max. 1.2 V Units CI CI() Notes: 6. Total IDD = IDDQ + IADD = FCK *CPD *VDDQ, solving for CPD = (IDDQ + IADD)/(FCK*VDDQ) where FCK is the input frequency, VDDQ is the power supply and CPD is the Power Dissipation Capacitance. 5 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory AC Specifications Parameter ten tdis tjit(cc+) tjit(cc-) t(O) t(O)dyn tsk(o) tjit(per) tjit(hper) slr(i) slr(o) VOX OE to and Y/Y OE to and Y/Y Cycle-to-cycle jitter Static phase offset Output clock skew Period jitter(12) (12) (11) Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)(15) Description Diagram see Fig 11 see Fig 11 see Fig 4 see Fig 5 see Fig 10 see Fig 6 see Fig 7 see Fig 8 see Fig 9 see Fig 9 (14, 16) AVDD, VDDQ = 1.8V 0.1V Min. Nom. Max. 8 8 0 0 -50 -50 -40 -75 1 0.5 1.5 (VDDQ/2) -0.1 2.5 3 (VDDQ/2) +0.1 2.5 40 -40 50 50 40 40 75 4 Units ns Dynamic phase offset ps Halk period jitter Input clock slew rate Output enable (OE) Output clock slew rate Outpu differenital-pair cross voltage(13) V/ns V see Fig 1, 9 see Fig 2 The PLL on the PI6CU877 is capable of meeting all the above test parameters while supporting SSC synthesirers with the following parameters: SSC modulation frequency SSC clock input frequency deviation PLL Loop Bandwidth 30.00 0.00 2.0 33 -0.50 kHz % MHz PI6CU877 PLL design should target the values below to minimize the SCC induced skew: Notes: 11. Static Phase Offset does not include Jitter 12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other. 13. VOX specified at the DRAM clock input or the test load. 14. To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock Input FBIN, FBIN are recommended to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these Nom values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered DDR2 DIMM application. 15. There are two terminations that are used with the above ac tests. The load/board in Figure 2 is used to measure the input and output differential-pair cross-voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables should be used. 16. The Output slew rate is determined from IBIS model load shown in Figure1. It is measured single-ended. 6 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory VDD PI6CU877 VCK R = 60 R = 60 VDD/2 VCK GND Figure 1. IBIS Model Output Load Figure 2. Output Load Test Circuit 1 VDD/2 C = 10pF -VDD/2 SCOPE Z= 60 R = 10 Z= 50 L= 2.97" Z= 60 R = 10 Z= 50 R = 50 VTT L= 2.97" R = 50 C = 10pF VTT PI6CU877 -VDD/2 -VDD/2 Note: VTT = GND Figure 3. Output Load Test Circuit 2 7 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Figure 4. Cycle-to-Cycle Jitter Figure 5. Static Phase Offset t sk(o) Figure 6. Output Skew 8 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Figure 7. Period Jitter (fo = average input frequency measured at CK/CK) Figure 8. Half-Period Jitter Figure 9. Input and Output Slew Rates 9 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Figure 10. Dynamic Phase Offset 50% VDD OE Y/Y OE ten Y 50% VDD Y 50% VDD Y Y tdis 50% VDD Figure 11. Time Delay Between Output Enable (OE) and Clock Output (Y, Y) 10 PS8689B 08/05/04 PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Packaging Mechanical: 52-Pin VFBGA (NF) Ordering Information Ordering Code PI6CU877NF PI6CU877NFE Package Code NF NF 52-ball VFBGA Pb-free & Green, 52-ball VFBGA Package Description Notes: 1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/ Pericom Semiconductor Corporation * 1-800-435-2336 * http://www.pericom.com 11 PS8689B 08/05/04 |
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